Synplify (synplify.exe)
Description
Synplify is an FPGA synthesis tool that translates hardware description languages (HDL) such as VHDL and Verilog into optimized gate-level netlists targeted for FPGA devices. It provides timing-driven synthesis, area and performance optimizations, constraint handling, and device-specific mapping to help designers meet timing, area, and power goals for FPGA implementations.
Used by digital and FPGA designers as part of the electronic design automation (EDA) flow, Synplify integrates with simulat...
Used by digital and FPGA designers as part of the electronic design automation (EDA) flow, Synplify integrates with simulat...
Statistics
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People using it:
16
Latest version:
Unknown
Keys:
20,047
Clicks:
61,194
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0
Time Used:
4d4h16m13s
Average Time Used:
6h16m1s
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